Field of the Invention
This invention relates to a jitter correction circuit and a flat panel display device provided with such a jitter correction circuit.
Flat panel display devices, such as liquid crystal display devices, have convenient features of thin thickness, light weight and low power consumption so that they have been widely used for image monitors in personal computers, word-processors and the like.
Many cathode ray tube (CRT) display devices are designed for displaying images in response to analogue video signals. The analogue video signals include sequential video signals indicative of brightness of pixels and vertical and horizontal synchronization signals. Where those video signals are applied to drive liquid crystal display devices, signal processing is indispensably performed to convert them into digital pixel data.
FIG. 9 is a block diagram of a signal conversion unit for processing such signals in a liquid crystal display device. An analogue video signal DATA1 with ordinarily 0.7 Vp-p (peak-to-peak voltage) is supplied to a signal amplifier circuit 1. This signal amplifier circuit 1 amplifies the video signal DATA1 to make it appropriate for an input level of an A/D converter circuit 2. The A/D converter circuit 2 converts the input video signal into a digital signal. This conversion is carried out in such a way that the video signal DATA1 is sampled in accordance with a dot clock signal reconstructed in a dot clock reconstruction circuit 3 as a sampling clock signal and that a pixel data is generated in response to every sampled level. The reconstructed dot check signal is synchronous with timing indicative of brightness at every pixel based upon the video signal DATA1. The dot clock signal is reconstructed from a horizontal synchronization signal Hsync, for instance, in the dot clock reconstruction circuit 3.
This dot clock reconstruction circuit 3 generally consists of a phase locked loop (PLL) circuit provided with a phase comparator, a loop filter, a voltage controlled oscillator and a divider. The voltage controlled oscillator provides an output signal which frequency and phase are controlled to be synchronous with the horizontal synchronization signal. The output signal is applied to the PLL circuit. The divider divides an output signal from the PLL circuit. The phase comparator compares the phase of an output signal of the divider circuit with that of the horizontal synchronization signal and detects error components. The loop filter eliminates unnecessary components and noises contained in an output signal from the phase comparator. At the same time, the loop filter also determines entire response characteristics of the PLL circuit. The voltage controlled oscillator is controlled in accordance with an output voltage of the loop filter. The output signal from the divider circuit is synchronized with the horizontal synchronization signal but it is not available to cause frequency and phase shifts with respect to the horizontal synchronization signal Hsync. The shifts occur at random and affect the reconstructed dot clock signal supplied from the dot clock reconstructed circuit 3 to the A/D conversion circuit 2 as the sampling clock signal. They result in jitters which randomly shift sampling timing of the video signal.
The relationship between pixel data derived from sampling of the video signal and sampling timing will be explained with reference to FIG. 10. Here, it is supposed that the video signal voltage varies between n[V] and m[V] and that pixel data are expressed by 4 bits. FIG. 10(a) shows that a sampling clock signal rises up at ideal sampling timing TA with respect to the video signal. This sampling timing is consistent with the center of each period of the video signal corresponding to each pixel. When the video signal voltage is m[V] at the sampling timing TA, this voltage is properly recognized and converted into pixel data of "1111".
Where the sampling clock signal, however, rises up at timing shifted from the sampling timing TA due to jitters as shown in FIGS. 10(b) and 10(c), the video signal voltage is mistakenly recognized as a value different from m[V]. FIG. 10(b) shows that the sampling clock signal rises up at the timing TB which is delayed from the timing TA. In this case, the video signal voltage is regarded as {n+7 (m-n)/16} [V], for instance, which is smaller than m[V] and converted into pixel data of "0111". FIG. 10(c) indicates a case where the sampling clock signal rises up at the timing TC which is advanced from the timing TA. The video signal voltage is recognized as {n+10(m-n)/16} [V] which is also smaller than m[V] and converted into pixel data of "1010".